Driving apparatus for driving a multi-phase load, a controller thereof and a control method thereof

ABSTRACT

A driving apparatus includes an inverter and a controller. The inverter converts, based on pulse width modulation (PWM) signals, an input voltage into output voltage signals that are used to drive a multi-phase load. The controller includes: a sequence generating module generating a first switching sequence and at least one second switching sequence based on duty cycle values; a selecting module selecting, to serve as a selected switching sequence, one of the first and second switching sequences that is determined to make phase currents which flow through the multi-phase load due to the output voltage signals have lowest total harmonic distortion; and an output generating module generates the PWM signals based on the selected switching sequence.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority of Taiwanese Patent Application No.105119854, filed on Jun. 24, 2016.

TECHNICAL FIELD

The disclosure relates to driving techniques, and more particularly to adriving apparatus for driving a multi-phase load, to a controllerthereof, and to a control method thereof.

BACKGROUND

A conventional driving apparatus uses space vector pulse widthmodulation (SVPWM) techniques to generate ten PWM signals with a PWMperiod that has a duration corresponding to a carrier frequency. Theconventional driving apparatus controls, based on each PWM signal,operation of a respective one of ten switches thereof between conductionand non-conduction, so as to convert a direct current (DC) input voltageinto five output voltage signals for driving a five-phase motor, therebygenerating five alternating current (AC) phase currents that flowthrough the five-phase motor. The phase currents have the samefundamental frequency that is lower than the carrier frequency, and anm^(th) one thereof lags a first one thereof by [72×(m−1)]° in phase,where 2≦m≦5.

In order to reduce the total harmonic distortion of the phase currents,the carrier frequency must be increased (i.e., the duration of the PWMperiod must be decreased). However, a higher carrier frequency leads tomore switchings and thus more switching loss for each switch, and tolower conversion efficiency of the conventional driving apparatus.

SUMMARY

Therefore, an object of the disclosure is to provide a driving apparatusthat can alleviate the drawback of the prior art, a controller thereofand a control method thereof.

According to one aspect of the disclosure, the driving apparatus is usedto drive a multi-phase load, and includes an inverter and a controller.The inverter is used to receive an input voltage, and receives aplurality of pulse width modulation (PWM) signals. The inverterconverts, based on the PWM signals, the input voltage into a pluralityof output voltage signals that are used to drive the multi-phase load.The controller includes a sequence generating module, a selecting moduleand an output generating module. The sequence generating module receivesa plurality of duty cycle values, and generates a first switchingsequence and at least one second switching sequence based on the dutycycle values. The selecting module is coupled to the sequence generatingmodule for receiving the first and second switching sequences therefrom.The selecting module selects, to serve as a selected switching sequence,one of the first and second switching sequences that is determined tomake a plurality of phase currents which flow through the multi-phaseload due to the output voltage signals have lowest total harmonicdistortion. The output generating module is coupled to the selectingmodule for receiving the selected switching sequence therefrom, and iscoupled further to the inverter. The output generating module generatesthe PWM signals for the inverter based on the selected switchingsequence. Each of the PWM signals is transitionable between a firststate and a second state. The first switching sequence corresponds tothat each of the PWM signals transitions two times during a PWM periodof the PWM signals. Each of the at least one second switching sequencecorresponds to that each of at least two of the PWM signals does nottransition during the PWM period, and that each of remaining ones of thePWM signals transitions at least two times during the PWM period. Atotal number of the transitions occurring in the PWM signals during thePWM period when any one of the at least one second switching sequence isselected equals a total number of the transitions occurring in the PWMsignals during the PWM period when the first switching sequence isselected.

According to another aspect of the disclosure, the controller is used tocontrol an inverter to convert an input voltage into a plurality ofoutput voltage signals for driving a multi-phase load. The controllerincludes a sequence generating module, a selecting module and an outputgenerating module. The sequence generating module receives a pluralityof duty cycle values, and generates a first switching sequence and atleast one second switching sequence based on the duty cycle values. Theselecting module is coupled to the sequence generating module forreceiving the first and second switching sequences therefrom. Theselecting module selects, to serve as a selected switching sequence, oneof the first and second switching sequences that is determined to make aplurality of phase currents which flow through the multi-phase load dueto the output voltage signals have lowest total harmonic distortion. Theoutput generating module is coupled to the selecting module forreceiving the selected switching sequence therefrom. The outputgenerating module generates, based on the selected switching sequence, aplurality of pulse width modulation (PWM) signals which are used tocontrol the inverter, and each of which is transitionable between afirst state and a second state. The first switching sequence correspondsto that each of the PWM signals transitions two times during a PWMperiod of the PWM signals. Each of the at least one second switchingsequence corresponds to that each of at least two of the PWM signalsdoes not transition during the PWM period, and that each of remainingones of the PWM signals transitions at least two times during the PWMperiod. A total number of the transitions occurring in the PWM signalsduring the PWM period when any one of the at least one second switchingsequence is selected equals a total number of the transitions occurringin the PWM signals during the PWM period when the first switchingsequence is selected.

According to yet another aspect of the disclosure, there is provided thecontrol method for controlling, using a controller, an inverter toconvert an input voltage into a plurality of output voltage signals fordriving a multi-phase load. The control method includes the steps of:generating, by the controller, a first switching sequence and at leastone second switching sequence based on a plurality of duty cycle values;selecting to serve as a selected switching sequence, by the controller,one of the first and second switching sequences that is determined tomake a plurality of phase currents which flow through the multi-phaseload due to the output voltage signals have lowest total harmonicdistortion; and generating based on the selected switching sequence, bythe controller, a plurality of pulse width modulation (PWM) signalswhich are used to control the inverter, and each of which istransitionable between a first state and a second state. The firstswitching sequence corresponds to that each of the PWM signalstransitions two times during a PWM period of the PWM signals. Each ofthe at least one second switching sequence corresponds to that each ofat least two of the PWM signals does not transition during the PWMperiod, and that each of remaining ones of the PWM signals transitionsat least two times during the PWM period. A total number of thetransitions occurring in the PWM signals during the PWM period when anyone of the at least one second switching sequence is selected equals atotal number of the transitions occurring in the PWM signals during thePWM period when the first switching sequence is selected.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the disclosure will become apparent inthe following detailed description of the embodiment with reference tothe accompanying drawings, of which:

FIG. 1 is a block diagram illustrating an embodiment of a drivingapparatus according to the disclosure in use with a five-phase load;

FIG. 2 is a circuit block diagram illustrating an inverter of theembodiment;

FIGS. 3 and 4 are block diagrams cooperatively illustrating a controllerof the embodiment;

FIG. 5 is a plot illustrating an exemplary first switching sequence ofthe embodiment;

FIGS. 6 to 9 are plots respectively illustrating four exemplary secondswitching sequences of the embodiment;

FIG. 10 is a timing diagram illustrating five pulse width modulation(PWM) signals of the embodiment that are generated when the exemplaryfirst switching sequence shown in FIG. 5 is selected;

FIG. 11 is a timing diagram illustrating the five PWM signals that aregenerated when the exemplary second switching sequence shown in FIG. 8is selected;

FIG. 12 is a flow chart illustrating a control method performed by thecontroller;

FIG. 13 is a plot illustrating a spectrum of a phase current that flowsthrough the five-phase load under a predetermined circumstance where thePWM signals are always generated based on the first switching sequence;

FIG. 14 is a plot illustrating a spectrum of the phase current in theembodiment; and

FIG. 15 is a plot illustrating total harmonic distortion versusamplitude characteristic under the predetermined circumstance and in theembodiment.

DETAILED DESCRIPTION

Referring to FIG. 1, an embodiment of a driving apparatus 10 accordingto the disclosure is used to drive an M-phase load 100 (e.g., an M-phasemotor in a wye or delta configuration). For illustration purposes, M=5in this embodiment. The driving apparatus 10 of this embodiment includesan inverter 1 and a controller 2.

Referring to FIG. 2, the inverter 1 is used to be coupled to a directcurrent (DC) power source 3 and the five-phase load 100. The inverter 1receives a DC input voltage (V_(dc)) from the DC power source 3, andfurther receives a number (2×M) (ten in this embodiment) of pulse widthmodulation (PWM) signals (γ₁-γ₅, γ₁ -γ₅ ). The inverter 1 converts,based on the PWM signals (γ₁-γ₅, γ₁ -γ₅ ), the input voltage (V_(dc))into a number (M) (five in this embodiment) of output voltage signals(V_(a)-V_(e)) that are used to drive the five-phase load 100, therebygenerating a number (M) (five in this embodiment) of phase currents(i_(aN)-i_(eN)) that flow through the five-phase load 100.

In this embodiment, the inverter 1 includes a number M (five in thisembodiment) of legs 11-15. Each leg 11-15 includes a first switch 111and a second switch 112 that are coupled to each other. The firstswitches 111 of the legs 11-15 are used to be coupled further to apositive terminal of the DC power source 3. The second switches 112 ofthe legs 11-15 are used to be coupled further to a negative terminal ofthe DC power source 3. The first and second switches 111, 112 of thelegs 11-15 respectively receive the PWM signals (γ₁-γ₅, γ₁ -γ₅ ), andare each operable between conduction and non-conduction based on therespective PWM signal (γ₁-γ₅, γ₁ -γ₅ ). Each output voltage signal(V_(a)-V_(e)) is provided at a common node between the first and secondswitches 111, 112 of a respective leg 11-15.

In this embodiment, each PWM signal (γ₁-γ₅, γ₁ -γ₅ ) is transitionablebetween a first state (e.g., a logic high level) that corresponds to theconduction of the respective switch 111, 112, and a second state (e.g.,a logic low level) that corresponds to the non-conduction of therespective switch 111, 112. For each leg 11-15, the two correspondingPWM signals (γ₁-γ₅, γ₁ -γ₅ ) are complementary to each other, such that:(a) when one of the first and second switches 111, 112 conducts, theother one of the first and second switches 111, 112 does not conduct;(b) when the first switch 111 conducts and the second switch 112 doesnot conduct, the respective output voltage signal (V_(a)-V_(e)) equalsthe input voltage (V_(dc)); and (c) when the first switch 111 does notconduct and the second switch 112 conducts, the respective outputvoltage signal (V_(a)-V_(e)) is zero. In other words, each outputvoltage signal (V_(a)-V_(e)) is transitionable between the input voltage(V_(dc)) and zero.

Referring to FIGS. 3 and 4, the controller 2 includes a referencegenerating module 21, an offset generating module 22, an adding module23, a sequence generating module 24, a selecting module 25 and an outputgenerating module 26.

Referring to FIG. 3, the reference generating module 21 generates anumber (M) (five in this embodiment) of reference values (r₁-r₅) thatrespectively correspond to a number (M) (five in this embodiment) ofpredetermined reference phase voltage curves. The predeterminedreference phase voltage curves have the same fundamental frequency of f₀and the same peak amplitude, and an m^(th) one thereof lags a first onethereof by [(360/M)×(m−1)]°([72×(m−1)]° in this embodiment) in phase,where 2≦m≦M (2≦m≦5 in this embodiment). Each reference value (r₁-r₅)changes over time, and sequentially equals samples of the respectivepredetermined reference phase voltage curve that are normalized to theinput voltage (V_(dc)), and that are taken at a carrier frequency off_(c) which is higher than the fundamental frequency of f₀ (i.e.,f_(c)>f₀). The peak amplitude of the predetermined reference phasevoltage curves is sufficient to make a difference between a maximum oneand a minimum one of the reference values (r₁-r₅) less than one (i.e.,max(r)−min(r)<1, where max(r) and min(r) respectively denote the maximumand minimum reference values).

The offset generating module 22 is coupled to the reference generatingmodule 21 for receiving the reference values (r₁-r₅) therefrom, andgenerates an offset value (V_(nN)) based on the reference values(r₁-r₅), where −min(r)<V_(nN)<1−max(r). In this embodiment,V_(nN)=0.5−0.5×[min(r)+max(r)].

The adding module 23 is coupled to the reference generating module 21for receiving the reference values (r₁-r₅) therefrom, and is coupledfurther to the offset generating module 22 for receiving the offsetvalue (V_(nN)) therefrom. The adding module 23 adds up each referencevalue (r₁-r₅) and the offset value (V_(nN)) to generate a respectiveduty cycle value (d₁-d₅) (i.e., d_(m)=r_(m)+V_(nN), where 1≦m≦5). Theoffset value (V_(nN)) makes each duty cycle value (d₁-d₅) greater thanzero and less than one (i.e., 0<d_(m)<1, where 1≦m≦5).

Referring to FIGS. 2 to 4, the sequence generating module 24 is coupledto the adding module 23 for receiving the duty cycle values (d₁-d₅)therefrom, and generates a first switching sequence and at least onesecond switching sequence based on the duty cycle values (d₁-d₅).

The selecting module 25 is coupled to the sequence generating module 24for receiving the first and second switching sequences therefrom, and iscoupled further to the reference generating module 21 for receiving thereference values (r₁-r₅) therefrom. Based on the first and secondswitching sequences and the reference values (r₁-r₅), the selectingmodule 25 selects, to serve as a selected switching sequence, one of thefirst and second switching sequences that is determined to make thephase currents (i_(aN)-i_(eN)) have lowest total harmonic distortion.

The output generating module 26 is coupled to the selecting module 25for receiving the selected switching sequence therefrom, and is coupledfurther to the first and second switches 111, 112 of the legs 11-15. Theoutput generating module 26 generates the PWM signals (γ₁-γ₅, γ₁ -γ₅ )respectively for the first and second switches 111, 112 of the legs11-15 based on the selected switching sequence.

Referring to FIGS. 5 to 9, in this embodiment, four second switchingsequences are generated, and each of the first and second switchingsequences corresponds to a respective PWM signal combination, which is acandidate for the combination of the PWM signals (γ₁-γ₅, γ₁ -γ₅ ) to beoutputted by the output generating module 26. As shown in FIG. 5, thefirst switching sequence includes a number (M+1) (six in thisembodiment) of vectors ({right arrow over (V₁)}-{right arrow over (V₆)})which are arranged sequentially, and each of which has a respectiveduration. As shown in FIGS. 6 to 9, each second switching sequenceincludes a number (M+1) (six in this embodiment) of vectors ({rightarrow over (V₁′)}-{right arrow over (V₆′)}) which are arrangedsequentially, and each of which has a respective duration.

Referring to FIGS. 2 and 5 to 9, in this embodiment, each vector ({rightarrow over (V₁)}-{right arrow over (V₆)}, {right arrow over(V₁′)}-{right arrow over (V₆′)}) includes a number (M) (five in thisembodiment) of bits (b₁-b₅) (i.e., {right arrow over (V_(m))} or {rightarrow over (V_(m)′)}=[b₁ b₂ b₃ b₄ b₅], where 1≦m≦6). In order tofacilitate description of this embodiment, [b₁ b₂ b₃ b₄ b₅] isalternatively expressed as a value of b₁×2⁴+b₂×2³+b₃×2²+b₄×2¹+b₅×2⁰hereinafter. For each of the first and second switching sequences, thebits (b₁-b₅) respectively represent the states of the PWM signals(γ₁-γ₅) in the respective PWM signal combination, and respectivelyrepresent the states of the PWM signals (γ₁ -γ₅ ) in the respective PWMsignal combination. Each bit (b₁-b₅) of, for example, logic ‘1’represents that the corresponding PWM signal (γ₁-γ₅) is at the firststate (i.e., the corresponding first switch 111 conducts), and that thecorresponding PWM signal (γ₁ -γ₅ ) is at the second state (i.e., thecorresponding second switch 112 does not conduct). Each bit (b₁-b₅) of,for example, logic ‘0’ represents that the corresponding PWM signal(γ₁-γ₅) is at the second state (i.e., the corresponding first switch 111does not conduct), and that the corresponding PWM signal (γ₁ -γ₅ ) is atthe first state (i.e., the corresponding second switch 112 conducts).

Referring to FIGS. 2 to 5 and Table 1 below, in this embodiment, thepredetermined reference phase voltage curves may result in a number(2×M) (ten in this embodiment) of different descending sequences of theduty cycle values (d₁-d₅) as shown in Table 1 below. For the firstswitching sequence, as shown in Table 1 below, a first one of thevectors ({right arrow over (V₁)}) is [0 0 0 0 0]=0, and an (m+1)^(th)one of the vectors ({right arrow over (V_(m+1))}) differs from an m^(th)one of the vectors ({right arrow over (V_(m))}) by one of the bits(b₁-b₅) that represents the state of one of the PWM signals (γ₁-γ₅)which has an m^(th) largest one of the duty cycle values (d₁-d₅) in thecorresponding PWM signal combination, where 1≦m≦5. For example, under acircumstance where d₁>d₂>d₅>d₃>d₄, the second vector ({right arrow over(V₂)}) is [1 0 0 0 0]=16 (i.e., differs from the first vector ({rightarrow over (V₁)}) by the bit (b₁) that corresponds to the PWM signal(γ₁) having the largest duty cycle value (d₁) in the corresponding PWMsignal combination), the third vector ({right arrow over (V₃)}) is [1 10 0 0]=24 (i.e., differs from the second vector ({right arrow over(V₂)}) by the bit (b₂) that corresponds to the PWM signal (γ₂) havingthe second largest duty cycle value (d₂) in the corresponding PWM signalcombination), the fourth vector ({right arrow over (V₄)}) is [1 1 0 01]=25 (i.e., differs from the third vector ({right arrow over (V₃)}) bythe bit (b₅) that corresponds to the PWM signal (γ₅) having the thirdlargest duty cycle value (d₅) in the corresponding PWM signalcombination), the fifth vector ({right arrow over (V₅)}) is [1 1 1 01]=29 (i.e., differs from the fourth vector ({right arrow over (V₄)}) bythe bit (b₃) that corresponds to the PWM signal (γ₃) having the fourthlargest duty cycle value (d₃) in the corresponding PWM signalcombination), and the sixth vector ({right arrow over (V₆)}) is [1 1 1 11]=31 (i.e., differs from the fifth vector ({right arrow over (V₅)}) bythe bit (b₄) that corresponds to the PWM signal (γ₄) having the fifthlargest duty cycle value (d₄) in the corresponding PWM signalcombination).

TABLE 1 first switching second switching arrangement sequence sequencesd₁ > d₂ > d₅ > d₃ > d₄ {0, 16, 24, 25, 29, 31} {16, 0, 16, 24, 25, 29}{24, 16, 24, 25, 29, 31} {0, 16, 24, 25, 29, 25} {16, 24, 25, 29, 31,29} d₂ > d₁ > d₃ > d₅ > d₄ {0, 8, 24, 28, 29, 31} {8, 0, 8, 24, 28, 29}{24, 8, 24, 28, 29, 31} {0, 8, 24, 28, 29, 28} {8, 24, 28, 29, 31, 29}d₂ > d₃ > d₁ > d₄ > d₅ {0, 8, 12, 28, 30, 31} {8, 0, 8, 12, 28, 30} {12,8, 12, 28, 30, 31} {0, 8, 12, 28, 30, 28} {8, 12, 28, 30, 31, 30} d₃ >d₂ > d₄ > d₁ > d₅ {0, 4, 12, 14, 30, 31} {4, 0, 4, 12, 14, 30} {12, 4,12, 14, 30, 31} {0, 4, 12, 14, 30, 14} {4, 12, 14, 30, 31, 30} d₃ > d₄ >d₂ > d₅ > d₁ {0, 4, 6, 14, 15, 31} {4, 0, 4, 6, 14, 15} {6, 4, 6, 14,15, 31} {0, 4, 6, 14, 15, 14} {4, 6, 14, 15, 31, 15} d₄ > d₃ > d₅ > d₂ >d₁ {0, 2, 6, 7, 15, 31} {2, 0, 2, 6, 7, 15} {6, 2, 6, 7, 15, 31} {0, 2,6, 7, 15, 7} {2, 6, 7, 15, 31, 15} d₄ > d₅ > d₃ > d₁ > d₂ {0, 2, 3, 7,23, 31} {2, 0, 2, 3, 7, 23} {3, 2, 3, 7, 23, 31} {0, 2, 3, 7, 23, 7} {2,3, 7, 23, 31, 23} d₅ > d₄ > d₁ > d₃ > d₂ {0, 1, 3, 19, 23, 31} {1, 0, 1,3, 19, 23} {3, 1, 3, 19, 23, 31} {0, 1, 3, 19, 23, 19} {1, 3, 19, 23,31, 23} d₅ > d₁ > d₄ > d₂ > d₃ {0, 1, 17, 19, 27, 31} {1, 0, 1, 17, 19,27} {17, 1, 17, 19, 27, 31} {0, 1, 17, 19, 27, 19} {1, 17, 19, 27, 31,27} d₁ > d₅ > d₂ > d₄ > d₃ {0, 16, 17, 25, 27, 31} {16, 0, 16, 17, 25,27} {17, 16, 17, 25, 27, 31} {0, 16, 17, 25, 27, 25} {16, 17, 25, 27,31, 27}

A vector of [0 0 0 0 0]=0 or [1 1 1 1 1]=31 is a so-called zero vectorwhich corresponds to that the output voltage signals (V_(a)-V_(e)) arethe same in magnitude, and that a number (M) (five in this embodiment)of line-to-line voltages (including V_(ab)=V_(a)-V_(b),V_(bc)=V_(b)-V_(c), V_(cd)=V_(c)-V_(d), V_(de)=V_(d)-V_(e) andV_(ea)=V_(e)-V_(a)) are all zero. A vector other than [0 0 0 0 0]=0 and[1 1 1 1 1]=31 is a so-called active vector which corresponds to that atleast one of the output voltage signals (V_(a)-V_(e)) is different fromremaining ones of the output voltage signals (V_(a)-V_(e)) in magnitude,and at least one of the line-to-line voltages (V_(ab), V_(bc), V_(cd),V_(de), V_(ea)) is not zero. It is known from Table 1 above that,regardless of the arrangement of the duty cycle values (d₁-d₅), thefirst and last vectors ({right arrow over (V₁)}, {right arrow over(V₆)}) of the first switching sequence are zero vectors, and remainingvectors ({right arrow over (V₂)}-{right arrow over (V₅)}) of the sameare active vectors.

In this embodiment, a PWM period of the PWM signals (γ₁-γ₅, γ₁ -γ₅ ) hasa duration of T_(pwm) that corresponds to the carrier frequency of f_(c)(i.e., T_(pwm)=1/f_(c)), and the durations of the vectors ({right arrowover (V₁)}-{right arrow over (V₆)}) of the first switching sequencewithin an early portion of the PWM period are respectivelyT₁={[V_(nN)+min(r)]/[1−max(r)+min(r)]}×(1−d_(1st))×T_(pwm)=[(1−d_(1st))/2]×T_(pwm),T₂=[(d_(1st)−d_(2nd))/2]×T_(pwm), T₃=[(d_(2nd)−d_(3rd))/2]×T_(pwm),T₄=[(d_(3rd)−d_(4th))/2]×T_(pwm), T₅=[(d_(4th)−d_(5th))/2]×T_(pwm) andT₆=(d_(5th)/2)×T_(pwm), where d_(1st) to d_(5th) respectively denote thefirst to fifth largest ones of the duty cycle values (d₁-d₅). Forexample, under the circumstance where d₁>d₂>d₅>d₃>d₄, d_(1st)=d₁,d_(2nd)=d₂, d_(3rd)=d₅, d_(4th)=d₃, d_(5th)=d₄, T₁=[(1−d₁)/2]×T_(pwm),T₂=[(d₁−d₂)/2]×T_(pwm), T₃=[(d₂−d₅)/2]×T_(pwm), T₄=[(d₅−d₃)/2]×T_(pwm),T₅=[(d₃−d₄)/2]×T_(pwm) and T₆=(d₄/2)×T_(pwm).

Referring to FIGS. 5 to 9 and Table 1 above, in this embodiment, one ofthe vectors ({right arrow over (V₁′)}-{right arrow over (V₆′)}) of eachsecond switching sequence is identical to one of the zero vectors({right arrow over (V₁)}, {right arrow over (V₆)}) of the firstswitching sequence, and the duration thereof equals a sum of thedurations of the zero vectors ({right arrow over (V₁)}, {right arrowover (V₆)}) of the first switching sequence; another two non-adjacentones of the vectors ({right arrow over (V₁′)}-{right arrow over (V₆′)})of each second switching sequence are each identical to the same one ofthe active vectors ({right arrow over (V₂)}-{right arrow over (V₅)}) ofthe first switching sequence, and a sum of the durations thereof equalsthe duration of said the same one of the active vectors ({right arrowover (V₂)}-{right arrow over (V₅)}) of the first switching sequence; andremaining ones of the vectors ({right arrow over (V₁′)}-{right arrowover (V₆′)}) of each second switching sequence are respectivelyidentical to remaining ones of the active vectors ({right arrow over(V₂)}-{right arrow over (V₅)}) of the first switching sequence, and thedurations thereof respectively equal the durations of said remainingones of the active vectors ({right arrow over (V₂)}-{right arrow over(V₅)}) of the first switching sequence.

In this embodiment, for a first one of the second switching sequenceswithin the early portion of the PWM period as exemplified in FIG. 6, thevector ({right arrow over (V₂′)}) is identical to the first vector({right arrow over (V₁)}) of the first switching sequence, and has theduration of T₂′=T₁+T₆; the non-adjacent vectors ({right arrow over(V₁′)}, {right arrow over (V₃′)}) are each identical to the secondvector ({right arrow over (V₂)}) of the first switching sequence, andrespectively have the durations of T₁′=T₂/2 and T₃′=T₂/2; and theremaining vectors ({right arrow over (V₄′)}-{right arrow over (V₆′)})are respectively identical to the third to fifth vectors ({right arrowover (V₃)}-{right arrow over (V₅)}) of the first switching sequence, andrespectively have the durations of T₄′=T₃, T₅′=T₄ and T₆′=T₅.

In this embodiment, for a second one of the second switching sequenceswithin the early portion of the PWM period as exemplified in FIG. 7, thevector ({right arrow over (V₆′)}) is identical to the last vector({right arrow over (V₆)}) of the first switching sequence, and has theduration of T₆′=T₁+T₆; the non-adjacent vectors ({right arrow over(V₁′)}, {right arrow over (V₃′)}) are each identical to the third vector({right arrow over (V₃)}) of the first switching sequence, andrespectively have the durations of T₁′=T₃/2 and T₃′=T₃/2; and theremaining vectors ({right arrow over (V₂′)}, {right arrow over (V₄′)},{right arrow over (V₅′)}) are respectively identical to the second,fourth and fifth vectors ({right arrow over (V₂)}, {right arrow over(V₄)}, {right arrow over (V₅)}) of the first switching sequence, andrespectively have the durations of T₂′=T₂, T₄′=T₄ and T₅′=T₅.

In this embodiment, for a third one of the second switching sequenceswithin the early portion of the PWM period as exemplified in FIG. 8, thevector ({right arrow over (V₆′)}) is identical to the first vector({right arrow over (V₁)}) of the first switching sequence, and has theduration of T₁′=T₁+T₆; the non-adjacent vectors ({right arrow over(V₄′)}, {right arrow over (V₆′)}) are each identical to theantepenultimate vector ({right arrow over (V₄)}) of the first switchingsequence, and respectively have the durations of T₄′=T₄/2 and T₆′=T₄/2;and the remaining vectors ({right arrow over (V₂′)}, {right arrow over(V₃′)}, {right arrow over (V₅′)}) are respectively identical to thesecond, third and fifth vectors ({right arrow over (V₂)}, {right arrowover (V₃)}, {right arrow over (V₅)}) of the first switching sequence,and respectively have the durations of T₂′=T₂, T₃′=T₃ and T₅′=T₅.

In this embodiment, for a fourth one of the second switching sequenceswithin the early portion of the PWM period as exemplified in FIG. 9, thevector ({right arrow over (V₅′)}) is identical to the last vector({right arrow over (V₆)}) of the first switching sequence, and has theduration of T₅′=T₁+T₆; the non-adjacent vectors ({right arrow over(V₄′)}, {right arrow over (V₆′)}) are each identical to the penultimatevector ({right arrow over (V₅)}) of the first switching sequence, andrespectively have the durations of T₄′=T₅/2 and T₆′=T₅/2; and theremaining vectors ({right arrow over (V₁′)}-{right arrow over (V₃′)})are respectively identical to the second to fourth vectors ({right arrowover (V₂)}-{right arrow over (V₄)}) of the first switching sequence, andrespectively have the durations of T₁′=T₂, T₂′=T₃ and T₃′=T₄.

It should be noted that the durations of the two non-adjacent vectors ofeach second switching sequence that correspond to the same vector of thefirst switching sequence are the same in this embodiment, but may bedifferent in other embodiments.

Referring to FIGS. 2 to 4, in this embodiment, the selecting module 25includes an estimating unit 251 and a selecting unit 252.

The estimating unit 251 is coupled to the sequence generating module 24for receiving the first and second switching sequences therefrom, and iscoupled further to the reference generating module 21 for receiving thereference values (r₁-r₅) therefrom. The estimating unit 251 estimates,based on the first and second switching sequences and the referencevalues (r₁-r₅), a plurality of current harmonic distortion factorsrespectively for the first and second switching sequences. The currentharmonic distortion factor (I_(HDF1)) corresponding to the firstswitching sequence may be estimated according to the following equation:

$I_{{HDF}\; 1} = {{\sum\limits_{m = 1}^{M + 1}i_{{err},m}} = {\sum\limits_{m = 1}^{M + 1}\left( {\frac{1}{L} \cdot {\int_{T_{m}}{{{{C_{M} \cdot \overset{\rightarrow_{T}}{V_{m}}} - {C_{M} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu}\ldots\mspace{14mu} r_{M}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} \right)}}$$\left( {I_{{HDF}\; 1} = {{\sum\limits_{m = 1}^{6}i_{{err},m}} = {\sum\limits_{m = 1}^{6}{\left( {\frac{1}{L} \cdot {\int_{T_{m}}{{{{C_{5} \cdot \overset{\rightarrow_{T}}{V_{m}}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} \right)\mspace{14mu}{in}\mspace{14mu}{this}\mspace{14mu}{embodiment}}}}} \right),$in this embodiment),and the current harmonic distortion factor (I_(HDF2)) corresponding toeach second switching sequence may be estimated according to thefollowing equation:

$I_{{HDF}\; 2} = {{\sum\limits_{m = 1}^{M + 1}i_{{err},m}} = {\sum\limits_{m = 1}^{M + 1}\left( {\frac{1}{L} \cdot {\int_{T_{m}^{\prime}}{{{{C_{M} \cdot \overset{\rightarrow_{T}}{V_{m}^{\prime}}} - {C_{M} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu}\ldots\mspace{14mu} r_{M}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} \right)}}$$\left( {I_{{HDF}\; 2} = {{\sum\limits_{m = 1}^{6}i_{{err},m}} = {\sum\limits_{m = 1}^{6}{\left( {\frac{1}{L} \cdot {\int_{T_{m}^{\prime}}{{{{C_{5} \cdot \overset{\rightarrow_{T}}{V_{m}^{\prime}}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} \right)\mspace{14mu}{in}\mspace{14mu}{this}\mspace{14mu}{embodiment}}}}} \right),$in this embodiment),where L denotes an inductance of the five-phase load 100,

${C_{M}\mspace{14mu}{is}\mspace{14mu}{an}\mspace{14mu}\left( {M\text{-}1} \right)\text{-}{by}\text{-}M\mspace{11mu}{matrix}\mspace{14mu}{and}\mspace{14mu}{equals}{\frac{2}{M} \cdot \begin{bmatrix}{\cos\; 0} & {\cos\;\theta} & {\cos\; 2\;\theta} & \ldots \\{\sin\; 0} & {\sin\;\theta} & {\sin\; 2\theta} & \ldots \\{\cos\; 0} & {\cos\; 2\theta} & {\cos\; 4\theta} & \ldots \\{\sin\; 0} & {\sin\; 2\theta} & {\sin\; 4\theta} & \ldots \\{\cos\; 0} & {\cos\; 3\theta} & {\cos\; 6\theta} & \ldots \\{\sin\; 0} & {\sin\; 3\theta} & {\sin\; 6\theta} & \ldots \\\vdots & \vdots & \vdots & \ddots\end{bmatrix}}\left( {C_{5} = {{\frac{2}{5} \cdot \begin{bmatrix}{\cos\; 0} & {\cos\;\theta} & {\cos\; 2\theta} & {\cos\; 3\theta} & {\cos\; 4\theta} \\{\sin\; 0} & {\sin\;\theta} & {\sin\; 2\theta} & {\sin\; 3\theta} & {\sin\; 4\theta} \\{\cos\; 0} & {\cos\; 2\theta} & {\cos\; 4\theta} & {\cos\; 6\theta} & {\cos\; 8\theta} \\{\sin\; 0} & {\sin\; 2\theta} & {\sin\; 4\theta} & {\sin\; 6\theta} & {\sin\; 8\theta}\end{bmatrix}}{in}\mspace{14mu}{this}\mspace{14mu}{embodiment}}} \right)},$in this embodiment), and θ=2π/M (θ=2π/5 in this embodiment). Forexample, under the circumstance where d₁>d₂>d₅>d₃>d₄, the currentharmonic distortion factor (I_(HDF1)) corresponding to the firstswitching sequence is estimated according to the following equation:

$\begin{matrix}{I_{{HDF}\; 1} = {{\frac{1}{L} \cdot {\int_{T_{1}}{{{{C_{5} \cdot \left\lbrack {0\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 0} \right\rbrack^{T}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} +}} \\{{\frac{1}{L} \cdot {\int_{T_{2}}{{{{C_{5} \cdot \left\lbrack {1\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 0} \right\rbrack^{T}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} +} \\{{\frac{1}{L} \cdot {\int_{T_{3}}{{{{C_{5} \cdot \left\lbrack {1\mspace{14mu} 1\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 0} \right\rbrack^{T}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} +} \\{{\frac{1}{L} \cdot {\int_{T_{4}}{{{{C_{5} \cdot \left\lbrack {1\mspace{14mu} 1\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 1} \right\rbrack^{T}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} +} \\{{\frac{1}{L} \cdot {\int_{T_{5}}{{{{C_{5} \cdot \left\lbrack {1\mspace{14mu} 1\mspace{14mu} 1\mspace{14mu} 0\mspace{14mu} 1} \right\rbrack^{T}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} +} \\{{\frac{1}{L} \cdot {\int_{T_{6}}{{{{C_{5} \cdot \left\lbrack {1\mspace{14mu} 1\mspace{14mu} 1\mspace{14mu} 1\mspace{14mu} 1} \right\rbrack^{T}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}},}\end{matrix}$the current harmonic distortion factor (I_(HDF2)) corresponding to thefirst one of the second switching sequences is estimated according tothe following equation:

$\begin{matrix}{I_{{HDF}\; 2} = {{\frac{1}{L} \cdot {\int_{T_{1}^{\prime}}{{{{C_{5} \cdot \left\lbrack {1\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 0} \right\rbrack^{T}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} +}} \\{{\frac{1}{L} \cdot {\int_{T_{2}^{\prime}}{{{{C_{5} \cdot \left\lbrack {0\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 0} \right\rbrack^{T}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} +} \\{{\frac{1}{L} \cdot {\int_{T_{3}^{\prime}}{{{{C_{5} \cdot \left\lbrack {1\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 0} \right\rbrack^{T}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} +} \\{{\frac{1}{L} \cdot {\int_{T_{4}^{\prime}}{{{{C_{5} \cdot \left\lbrack {1\mspace{14mu} 1\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 0} \right\rbrack^{T}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} +} \\{{\frac{1}{L} \cdot {\int_{T_{5}^{\prime}}{{{{C_{5} \cdot \left\lbrack {1\mspace{14mu} 1\mspace{14mu} 0\mspace{14mu} 0\mspace{14mu} 1} \right\rbrack^{T}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}} +} \\{{\frac{1}{L} \cdot {\int_{T_{6}^{\prime}}{{{{C_{5} \cdot \left\lbrack {1\mspace{14mu} 1\mspace{14mu} 1\mspace{14mu} 0\mspace{14mu} 1} \right\rbrack^{T}} - {C_{5} \cdot \left\lbrack {r_{1}\mspace{14mu} r_{2}\mspace{14mu} r_{3}\mspace{14mu} r_{4}\mspace{14mu} r_{5}} \right\rbrack^{T}}}}_{2}^{2}d\; t}}},}\end{matrix}$and so on.

The selecting unit 252 is coupled to the sequence generating module 24for receiving the first and second switching sequences therefrom, iscoupled further to the estimating unit 251 for receiving the currentharmonic distortion factors therefrom, and is coupled further to theoutput generating module 26. The selecting unit 252 compares the currentharmonic distortion factors, and selects one of the first and secondswitching sequences that corresponds to a minimum one of the currentharmonic distortion factors to serve as the selected switching sequencefor the output generating module 26.

Referring to FIGS. 10 and 11, in this embodiment, during the PWM periodthat has the duration of T_(pwm), the PWM signals (γ₁-γ₅) change overtime, and sequentially correspond to the first vector ({right arrow over(V₁)} or {right arrow over (V₁′)}) of the selected switching sequencefor the duration of T₁ or T₁′, the second vector ({right arrow over(V₂)} or {right arrow over (V₂′)}) of the selected switching sequencefor the duration T₂ or T₂′, . . . so on and so forth to the last vector({right arrow over (V₆)} or {right arrow over (V₆′)}) of the selectedswitching sequence for the duration of T₆ or T₆′, the last vector({right arrow over (V₆)} or {right arrow over (V₆′)}) of the selectedswitching sequence for a duration of T₆″ or T₆′″, the penultimate vector({right arrow over (V₅)} or {right arrow over (V₅′)}) of the selectedswitching sequence for a duration of T₅″ or T₅′″, . . . so on and soforth to the first vector ({right arrow over (V₁)} or {right arrow over(V₁′)}) of the selected switching sequence for a duration of T₁″ orT₁′″, and so do the PWM signals (γ₁ -γ₅ ). When the first switchingsequence is selected, the second correspondence of the PWM signals(γ₁-γ₅) to the first vector ({right arrow over (V₁)}) lasts for theduration of T₁″=(1−d_(1st))×T_(pwm)−T₁=T₁, the second correspondence ofthe PWM signals (γ₁-γ₅) to the second vector ({right arrow over (V₂)})lasts for the duration of T₂″=T₂, the second correspondence of the PWMsignals (γ₁-γ₅) to the third vector ({right arrow over (V₃)}) lasts forthe duration of T₃″=T₃, the second correspondence of the PWM signals(γ₁-γ₅) to the fourth vector ({right arrow over (V₄)}) lasts for theduration of T₄″=T₄, the second correspondence of the PWM signals (γ₁-γ₅)to the pentuliamte vector ({right arrow over (V₅)}) lasts for theduration of T₅″=T₅, and the second correspondence of the PWM signals(γ₁-γ₅) to the last vector ({right arrow over (V₆)}) lasts for theduration of T₆″=T₆. When the selected switching sequence is any one ofthe second switching sequences, the second correspondence of the PWMsignals (γ₁-γ₅) to the vectors ({right arrow over (V₁′)}-{right arrowover (V₆′)}) last the durations of T₁′″ to T₆′″, respectively, with thedurations of T₁′″ to T₆′″ defined as follows. When the first one of thesecond switching sequences is selected, T₁′″=T₁′,T₂′″=(1−d_(1st)+d_(5th))×T_(pwm)−T₂′=T₂′, T₃′″=T₃′, T₄′″=T₄′, T₅′″=T₅′and T₆′″=T₆′. When the second one of the second switching sequences isselected, T₁′″=T₁′, T₂′″=T₂′, T₃′″=T₃′, T₄′″=T₄′, T₅′″=T₅′ andT₆′″=(1−d_(1st)+d_(5th))×T_(pwm)−T₆′=T₆′. When the third one of thesecond switching sequences is selected,T₁′″=(1−d_(1st)+d_(5th))×T_(pwm)−T₁′=T₁′, T₂′″=T₂′, T₃′″=T₃′, T₄′″=T₄′,T₅′″=T₅′ and T₆′″=T₆′. When the fourth one of the second switchingsequences is selected, T₁′″=T₁′, T₂′″=T₂′, T₃′″=T₃′, T₄′″=T₄′,T₅′″=(1−d_(1st)+d_(5th))×T_(pwm)−T₅′=T₅′″ and T₆′″=T₆′. For example,under the circumstance where d₁>d₂>d₅>d₃>d₄, the PWM signals (γ₁-γ₅)that are generated when the first switching sequence shown in FIG. 5 isselected are depicted in FIG. 10, and the PWM signals (γ₁-γ₅) that aregenerated when the third one of the second switching sequences shown inFIG. 8 is selected are depicted in FIG. 11.

It should be noted that: (a) as exemplified in FIG. 10, the firstswitching sequence corresponds to that each PWM signal (γ₁-γ₅, γ₁ -γ₅ )transitions two times during the PWM period; (b) as exemplified in FIG.11, each second switching sequence corresponds to that each of at leasttwo complementary ones of the PWM signals (γ₁-γ₅, γ₁ -γ₅ ) does nottransition during the PWM period, and that each of remaining ones of thePWM signals (γ₁-γ₅, γ₁ -γ₅ ) transitions at least two times during thePWM period; and (c) a total number of the transitions during the PWMperiod when any one of the at least one second switching sequence isselected equals a total number of the transitions during the PWM periodwhen the first switching sequence is selected (i.e., 4×M (twenty in thisembodiment)).

In this embodiment, as exemplified in FIG. 11, each second switchingsequence corresponds to that each of two complementary ones of the PWMsignals (γ₁-γ₅, γ₁ -γ₅ ) does not transition during the PWM period, thateach of another two complementary ones of the PWM signals (γ₁-γ₅, γ₁ -γ₅) transitions four times during the PWM period, and that each of theother ones of the PWM signals (γ₁-γ₅, γ₁ -γ₅ ) transitions two timesduring the PWM period.

As a result, the phase currents (i_(aN)-i_(eN)) are AC phase currentsthat have substantially the same fundamental frequency of f₀ andsubstantially the same peak amplitude, and an m^(th) one thereof lags afirst one thereof by substantially [72×(m−1)]° in phase, where 2≦m≦5.

Referring to FIGS. 2 to 4 and 12, a control method performed by thecontroller 2 includes the following steps (A-C).

In step (A), the sequence generating module 24 generates the first andsecond switching sequences based on the duty cycle values (d₁-d₅).

In step (B), based on the first and second switching sequences and thereference values (r₁-r₅), the selecting module 25 selects, to serve asthe selected switching sequence, one of the first and second switchingsequences that is determined to make the phase currents (i_(aN)-i_(eN))have the lowest total harmonic distortion.

In this embodiment, step (B) includes the following sub-steps (B1-B3).

In sub-step (B1), the estimating unit 251 estimates, based on the firstand second switching sequences and the reference values (r₁-r₅), thecurrent harmonic distortion factors respectively for the first andsecond switching sequences.

In sub-step (B2), the selecting unit 252 compares the current harmonicdistortion factors.

In sub-step (B3), the selecting unit 252 selects one of the first andsecond switching sequences that corresponds to the minimum one of thecurrent harmonic distortion factors to serve as the selected switchingsequence.

In step (C), the output generating module 26 generates the PWM signals(γ₁-γ₅, γ₁ -γ₅ ) based on the selected switching sequence.

3With the predetermined reference phase voltage curves having the samepeak amplitude of 0.5×V_(dc) and the same fundamental frequency of f₀=60Hz, a spectrum of one of the phase currents (i_(aN)-i_(eN)) under apredetermined circumstance where the first switching sequence is alwaysselected is depicted in FIG. 13, and the spectrum of said one of thephase currents (i_(aN)-i_(eN)) in this embodiment is depicted in FIG.14. It is known from FIGS. 13 and 14 that harmonics of said one of thephase currents (i_(aN)-i_(eN)) around 10⁴ Hz to 10⁵ Hz are lower in thisembodiment than those under the predetermined circumstance.

FIG. 15 illustrates the relationship between the total harmonicdistortion of the phase currents (i_(aN)-i_(eN)) and the peak amplitudeof the predetermined reference phase voltage curves (normalized to theinput voltage (V_(dc))) under the predetermined circumstance and that inthis embodiment. It is known from FIG. 15 that, when the peak amplitudeof the predetermined reference phase voltage curves is 0.5×V_(dc), thetotal harmonic distortion of the phase currents (i_(aN)-i_(eN)) in thisembodiment is reduced by 22% as compared to that under the predeterminedcircumstance.

In view of the above, since the controller 2 generates a plurality ofswitching sequences that correspond to the same total number of thetransitions of the PWM signals (γ₁-γ₅, γ₁ -γ₅ ) during the PWM period,and since the controller 2 generates the PWM signals (γ₁-γ₅, γ₁ -γ₅ )based on one of the switching sequences that is determined to make thephase currents (i_(aN)-i_(eN)) have the lowest total harmonicdistortion, the total harmonic distortion of the phase currents(i_(aN)-i_(eN)) may be reduced without increasing the carrier frequency.

It should be noted that, in other embodiments, M may be an integer thatis greater than two and that is other than five. In an example whereM=3, the first switching sequence may be {{right arrow over (V₁)},{right arrow over (V₂)}, {right arrow over (V₃)}, {right arrow over(V₄)}}, and the second switching sequences may respectively be {{rightarrow over (V₂)}, {right arrow over (V₁)}, {right arrow over (V₂)},{right arrow over (V₃)}}, {{right arrow over (V₃)}, {right arrow over(V₂)}, {right arrow over (V₃)}, {right arrow over (V₄)}}, {{right arrowover (V₁)}, {right arrow over (V₂)}, {right arrow over (V₃)}, {rightarrow over (V₂)}} and {{right arrow over (V₂)}, {right arrow over (V₃)},{right arrow over (V₄)}, {right arrow over (V₃)}}. In another examplewhere M=7, the first switching sequence may be {{right arrow over (V₁)},{right arrow over (V₂)}, {right arrow over (V₃)}, {right arrow over(V₄)}, {right arrow over (V₅)}, {right arrow over (V₆)}, {right arrowover (V₇)}, {right arrow over (V₈)}}, and the second switching sequencesmay respectively be {{right arrow over (V₂)}, {right arrow over (V₁)},{right arrow over (V₂)}, {right arrow over (V₃)}, {right arrow over(V₄)}, {right arrow over (V₅)}, {right arrow over (V₆)}, {right arrowover (V₇)}}, {{right arrow over (V₃)}, {right arrow over (V₂)}, {rightarrow over (V₃)}, {right arrow over (V₄)}, {right arrow over (V₅)},{right arrow over (V₆)}, {right arrow over (V₇)}, {right arrow over(V₈)}}, {{right arrow over (V₁)}, {right arrow over (V₂)}, {right arrowover (V₃)}, {right arrow over (V₄)}, {right arrow over (V₅)}, {rightarrow over (V₆)}, {right arrow over (V₇)}, {right arrow over (V₆)}} and{{right arrow over (V₂)}, {right arrow over (V₃)}, {right arrow over(V₄)}, {right arrow over (V₅)}, {right arrow over (V₆)}, {right arrowover (V₇)}, {right arrow over (V₈)}, {right arrow over (V₇)}}.

In the description above, for the purposes of explanation, numerousspecific details have been set forth in order to provide a thoroughunderstanding of the embodiment. It will be apparent, however, to oneskilled in the art, that one or more other embodiments may be practicedwithout some of these specific details. It should also be appreciatedthat reference throughout this specification to“one embodiment,” “anembodiment,” an embodiment with an indication of an ordinal number andso forth means that a particular feature, structure, or characteristicmay be included in the practice of the disclosure. It should be furtherappreciated that in the description, various features are sometimesgrouped together in a single embodiment, figure, or description thereoffor the purpose of streamlining the disclosure and aiding in theunderstanding of various inventive aspects.

While the disclosure has been described in connection with what isconsidered the exemplary embodiment, it is understood that thedisclosure is not limited to the disclosed embodiment but is intended tocover various arrangements included within the spirit and scope of thebroadest interpretation so as to encompass all such modifications andequivalent arrangements.

What is claimed is:
 1. A driving apparatus used to drive a multi-phaseload, said driving apparatus comprising: an inverter used to receive aninput voltage, and receiving a plurality of pulse width modulation (PWM)signals, said inverter converting, based on the PWM signals, the inputvoltage into a plurality of output voltage signals that are used todrive the multi-phase load; and a controller including a sequencegenerating module receiving a plurality of duty cycle values, andgenerating a first switching sequence and at least one second switchingsequence based on the duty cycle values, a selecting module coupled tosaid sequence generating module for receiving the first and secondswitching sequences therefrom, said selecting module selecting, to serveas a selected switching sequence, one of the first and second switchingsequences that is determined to make a plurality of phase currents whichflow through the multi-phase load due to the output voltage signals havelowest total harmonic distortion, and an output generating modulecoupled to said selecting module for receiving the selected switchingsequence therefrom, and coupled further to said inverter, said outputgenerating module generating the PWM signals for said inverter based onthe selected switching sequence, each of the PWM signals beingtransitionable between a first state and a second state; wherein thefirst switching sequence corresponds to that each of the PWM signalstransitions two times during a PWM period of the PWM signals; whereineach of the at least one second switching sequence corresponds to thateach of at least two of the PWM signals does not transition during thePWM period, and that each of remaining ones of the PWM signalstransitions at least two times during the PWM period; and wherein atotal number of the transitions occurring in the PWM signals during thePWM period when any one of the at least one second switching sequence isselected equals a total number of the transitions occurring in the PWMsignals during the PWM period when the first switching sequence isselected.
 2. The driving apparatus of claim 1, wherein each of the atleast one second switching sequence corresponds to that each of two ofthe PWM signals does not transition during the PWM period, that each ofanother two of the PWM signals transitions four times during the PWMperiod, and that each of the other ones of the PWM signals transitionstwo times during the PWM period.
 3. The driving apparatus of claim 1,wherein: the first switching sequence includes a plurality of vectorswhich are arranged sequentially, a first one and a last one of which arezero vectors, and remaining ones of which are active vectors; and eachof the at least one second switching sequence includes a plurality ofvectors which are sequentially arranged, one of which is identical toone of the zero vectors of the first switching sequence, another twonon-adjacent ones of which are each identical to a same one of theactive vectors of the first switching sequence, and remaining ones ofwhich are respectively identical to remaining ones of the active vectorsof the first switching sequence.
 4. The driving apparatus of claim 3,wherein: each of the vectors of the first and second switching sequenceshas a respective duration; and for each of the at least one secondswitching sequence, the duration of said one of the vectors thereofequals a sum of the durations of the zero vectors of the first switchingsequence, a sum of the durations of said another two non-adjacent onesof the vectors thereof equals the duration of said the same one of theactive vectors of the first switching sequence, and the durations ofsaid remaining ones of the vectors thereof respectively equal thedurations of the remaining ones of the active vectors of the firstswitching sequence.
 5. The driving apparatus of claim 3, wherein for oneof the at least one second switching sequence, said one of the vectorsthereof is a second one of the vectors thereof, and is identical to thefirst one of the vectors of the first switching sequence, and saidanother two non-adjacent ones of the vectors thereof are respectively afirst one and a third one of the vectors thereof, and are each identicalto a second one of the vectors of the first switching sequence.
 6. Thedriving apparatus of claim 3, wherein for one of the at least one secondswitching sequence, said one of the vectors thereof is a last one of thevectors thereof, and is identical to the last one of the vectors of thefirst switching sequence, and said another two non-adjacent ones of thevectors thereof are respectively a first one and a third one of thevectors thereof, and are each identical to a third one of the vectors ofthe first switching sequence.
 7. The driving apparatus of claim 3,wherein for one of the at least one second switching sequence, said oneof the vectors thereof is a first one of the vectors thereof, and isidentical to the first one of the vectors of the first switchingsequence, and said another two non-adjacent ones of the vectors thereofare respectively an antepenultimate one and a last one of the vectorsthereof, and are each identical to an antepenultimate one of the vectorsof the first switching sequence.
 8. The driving apparatus of claim 3,wherein for one of the at least one second switching sequence, said oneof the vectors thereof is a penultimate one of the vectors thereof, andis identical to the last one of the vectors of the first switchingsequence, and said another two non-adjacent ones of the vectors thereofare respectively an antepenultimate one and a last one of the vectorsthereof, and are each identical to a penultimate one of the vectors ofthe first switching sequence.
 9. The driving apparatus of claim 1,wherein said selecting module includes: an estimating unit coupled tosaid sequence generating module for receiving the first and secondswitching sequences therefrom, said estimating unit estimating aplurality of current harmonic distortion factors respectively for thefirst and second switching sequences; and a selecting unit coupled tosaid sequence generating module for receiving the first and secondswitching sequences therefrom, coupled further to said estimating unitfor receiving the current harmonic distortion factors therefrom, andcoupled further to said output generating module, said selecting unitcomparing the current harmonic distortion factors, and selecting one ofthe first and second switching sequences that corresponds to a minimumone of the current harmonic distortion factors to serve as the selectedswitching sequence for said output generating module.
 10. A controllerused to control an inverter to convert an input voltage into a pluralityof output voltage signals for driving a multi-phase load, saidcontroller comprising: a sequence generating module receiving aplurality of duty cycle values, and generating a first switchingsequence and at least one second switching sequence based on the dutycycle values; a selecting module coupled to said sequence generatingmodule for receiving the first and second switching sequences therefrom,said selecting module selecting, to serve as a selected switchingsequence, one of the first and second switching sequences that isdetermined to make a plurality of phase currents which flow through themulti-phase load due to the output voltage signals have lowest totalharmonic distortion; and an output generating module coupled to saidselecting module for receiving the selected switching sequencetherefrom, said output generating module generating, based on theselected switching sequence, a plurality of pulse width modulation (PWM)signals which are used to control the inverter, and each of which istransitionable between a first state and a second state; wherein thefirst switching sequence corresponds to that each of the PWM signalstransitions two times during a PWM period of the PWM signals; whereineach of the at least one second switching sequence corresponds to thateach of at least two of the PWM signals does not transition during thePWM period, and that each of remaining ones of the PWM signalstransitions at least two times during the PWM period; and wherein atotal number of the transitions occurring in the PWM signals during thePWM period when any one of the at least one second switching sequence isselected equals a total number of the transitions occurring in the PWMsignals during the PWM period when the first switching sequence isselected.
 11. The controller of claim 10, wherein each of the at leastone second switching sequence corresponds to that each of two of the PWMsignals does not transition during the PWM period, that each of anothertwo of the PWM signals transitions four times during the PWM period, andthat each of the other ones of the PWM signals transitions two timesduring the PWM period.
 12. The controller of claim 10, wherein: thefirst switching sequence includes a plurality of vectors which arearranged sequentially, a first one and a last one of which are zerovectors, and remaining ones of which are active vectors; and each of theat least one second switching sequence includes a plurality of vectorswhich are sequentially arranged, one of which is identical to one of thezero vectors of the first switching sequence, another two non-adjacentones of which are each identical to a same one of the active vectors ofthe first switching sequence, and remaining ones of which arerespectively identical to remaining ones of the active vectors of thefirst switching sequence.
 13. The controller of claim 12, wherein: eachof the vectors of the first and second switching sequences has arespective duration; and for each of the at least one second switchingsequence, the duration of said one of the vectors thereof equals a sumof the durations of the zero vectors of the first switching sequence, asum of the durations of said another two non-adjacent ones of thevectors thereof equals the duration of said the same one of the activevectors of the first switching sequence, and the durations of saidremaining ones of the vectors thereof respectively equal the durationsof the remaining ones of the active vectors of the first switchingsequence.
 14. The controller of claim 10, wherein said selecting moduleincludes: an estimating unit coupled to said sequence generating modulefor receiving the first and second switching sequences therefrom, saidestimating unit estimating a plurality of current harmonic distortionfactors respectively for the first and second switching sequences; and aselecting unit coupled to said sequence generating module for receivingthe first and second switching sequences therefrom, coupled further tosaid estimating unit for receiving the current harmonic distortionfactors therefrom, and coupled further to said output generating module,said selecting unit comparing the current harmonic distortion factors,and selecting one of the first and second switching sequences thatcorresponds to a minimum one of the current harmonic distortion factorsto serve as the selected switching sequence for said output generatingmodule.
 15. A control method for controlling, using a controller, aninverter to convert an input voltage into a plurality of output voltagesignals for driving a multi-phase load, said control method comprisingsteps of: generating, by the controller, a first switching sequence andat least one second switching sequence based on a plurality of dutycycle values; selecting to serve as a selected switching sequence, bythe controller, one of the first and second switching sequences that isdetermined to make a plurality of phase currents which flow through themulti-phase load due to the output voltage signals have lowest totalharmonic distortion; and generating based on the selected switchingsequence, by the controller, a plurality of pulse width modulation (PWM)signals which are used to control the inverter, and each of which istransitionable between a first state and a second state; wherein thefirst switching sequence corresponds to that each of the PWM signalstransitions two times during a PWM period of the PWM signals; whereineach of the at least one second switching sequence corresponds to thateach of at least two of the PWM signals does not transition during thePWM period, and that each of remaining ones of the PWM signalstransitions at least two times during the PWM period; and wherein atotal number of the transitions occurring in the PWM signals during thePWM period when any one of the at least one second switching sequence isselected equals a total number of the transitions occurring in the PWMsignals during the PWM period when the first switching sequence isselected.
 16. The control method of claim 15, wherein each of the atleast one second switching sequence corresponds to that each of two ofthe PWM signals does not transition during the PWM period, that each ofanother two of the PWM signals transitions four times during the PWMperiod, and that each of the other ones of the PWM signals transitionstwo times during the PWM period.
 17. The control method of claim 15,wherein: the first switching sequence includes a plurality of vectorswhich are arranged sequentially, a first one and a last one of which arezero vectors, and remaining ones of which are active vectors; and eachof the at least one second switching sequence includes a plurality ofvectors which are sequentially arranged, one of which is identical toone of the zero vectors of the first switching sequence, another twonon-adjacent ones of which are each identical to a same one of theactive vectors of the first switching sequence, and remaining ones ofwhich are respectively identical to remaining ones of the active vectorsof the first switching sequence.
 18. The control method of claim 17,wherein: each of the vectors of the first and second switching sequenceshas a respective duration; and for each of the at least one secondswitching sequence, the duration of said one of the vectors thereofequals a sum of the durations of the zero vectors of the first switchingsequence, a sum of the durations of said another two non-adjacent onesof the vectors thereof equals the duration of said the same one of theactive vectors of the first switching sequence, and the durations ofsaid remaining ones of the vectors thereof respectively equal thedurations of the remaining ones of the active vectors of the firstswitching sequence.
 19. The control method of claim 15, wherein the stepof selecting includes sub-steps of: estimating a plurality of currentharmonic distortion factors respectively for the first and secondswitching sequences; comparing the current harmonic distortion factors;and selecting one of the first and second switching sequences thatcorresponds to a minimum one of the current harmonic distortion factorsto serve as the selected switching sequence.